Block Diagrams for Cyclic Coder

Block Diagrams

for Cyclic Coder

We wish to implement the encoder of cyclic code. The implementation of (n, k) cyclic code involves the division of  x^n-k d(x) by g(x) and can be implemented by a dividing circuit , which is a shift register with feedback connections according to the generator polynomial

              g(x) = x^n-k + g₁ x^n-k-1 + ………………+ g_n-k-1 x + 1

 

The operation of the block diagram can be subdivided into tow parts

1- Input represented by shift register which used to receive the transmitted data in parallel form and getting it at its out in serial form

2-Control represented by the counter it controls all parts in the circuit and it. Its function as follow

·        It controls the cyclic period to 7 clocks. So it cyclically counts to number 7.

·        Controlling loading data. As the Q₆ of the counter is connected to PE (parallel enable) of shift register via inverter, that means

·        When Q6 is high the PE is low that makes shift register to operate in parallel mode .

·         At all other remaining clocks, the PE is low which make the shift register to operate in serial mode .

·        Controlling the division circuit(flip-flop + control gate ).The first 4 clocks are connected to OR gate. Which means the output of the OR gate will be high during the first 4 clocks. The output of OR gate is connected to control gate of division circuit (AND gate).

·         The control gate will be on during first 4 clocks which allow to all transmitted data to entered flip-flops. For remaining 3 clocks the control gate will be off to get out the parity bits that formed in flip-flops.

·        Switching circuit which consists of(two AND gate & OR gate)

during first 4 clocks the gate 1 is on while gate 2 is off that allow to data to out during these clocks. While for the next three clocks the gate 2 will be on and gate 1 is off which allow the content of the flip-flops to out.

   

After each 7’clock the system is ready to reload new data and process it.