Circuit Diagram for Polar Signaling

Circuit Diagram for
Polar Signaling

Circuit Components

• IC 555 Timer
• 40195 (4- BIT UNIVERSAL SHIFT REGISTER)
• 4017 (5- STAGE JOHNSON COUNTER)
• 4081 (QUADRUPLE 2- INPUT AND GATE)
• 4069 (HEX INVERTER)
• 741 (OP- AMP)
• Resistors                                                               

Connection Of Circuit

Data Generation

To obtain a stream of pulses which are repeated periodically to fed the circuit all time, the connection of IC's as follow:

Ring Counter

• The counter is adjusted to count 4 clocks by connecting a Q₄ pin with a reset pin of the counter.
• We will use the positive edge clock (cp0) so (cp1') is earthed.                                                             
• The Q₀ pin is connected to Inverter gate and the output of the Inverter is connected to the PE' pin of the shift register to convert it from parallel to serial mode.

Shift Register

• The shift register is adjusted to work in parallel to serial mode by making J and K' LOW and the MR' is HIGH to get the outputs all times.
• The stream of pulses are obtained from Q₃ pin of shift register.

Line Code Circuit

• Transmitted data are entered to the circuit as a NRZ binary signal.
• Transmitted data are applied to one input of a lower AND  gate.
• The inverting of transmitted data are applied to one input of an upper  AND gate.
• The second input of the two AND gates is the clock of the circuit.

• The two outputs of the two AND gates are applied to a subtractor circuit.
• The output of subtractor is a RZ polar signal.

Data Recovery Circuit

• The output of the subtractor is applied to the two inputs of an AND gate.

Clock Recovery Circuit

• The output of  subtractor is applied to a full wave rectifier circuit.
• The output of the rectifier circuit is the clock signal.

The Operation Of The Circuit

• First the data are entered to the circuit as a NRZ binary signal.
• The output of lower AND gate is the same data as a RZ binary signal.
• The output of upper AND gate is the inverting of data as a RZ binary signal.
• The Op- Amp circuit (subtractor) is used to subtract the output of upper AND gate from the output of lower AND gate.
• Now the output of subtractor is a RZ polar signal.
• If the clock is replaced by a HIGH dc voltage the output of subtractor is a NRZ polar signal.
• The output of AND gate #3 is the data because any logic gate consider the negative voltage as same as a logic 0.
• The output of the full wave rectifier circuit is the clock of the circuit.